CMOS Transistor for Ultra-Low-Power ICs
Semiconductors today burn too much power. And excess power consumption prevents integrated circuit (IC) designers from incorporating additional functionality and capabilities. For many years CMOS transistors have been stuck against a supply voltage “wall” of around 1 Volt.
To get past this power problem, the industry must re-think every aspect of electronic design – including the structure of the transistor.
|Video: Planar, bulk CMOS advanced device technology|
Following Moore’s Law scaling, the power supply voltage of CMOS has been reduced progressively down to the 130nm technology node. However, power supply voltages have remained at around1.0V even though process technologies have continued to scale from 130nm to 28nm. Since power consumption is a function of voltage squared (V2) or voltage cubed (V3), voltage scaling has become a primary issue for CMOS technology. Scaling of supply voltage stopped at the 130nm node because of threshold voltage (VT) variation which is primarily caused by random dopant fluctuation (RDF). RDF is a form of device and process variation resulting from fluctuations in the concentration of the implanted dopant or impurity atoms in the transistor channel.
To control VT variability, the industry needs a new device structure. Several fully depleted advanced device technologies have emerged to address VT variability, including FDSOI and Tri-Gate – a FinFET technology. For the mobile market, both cost and power considerations for system on chip (SOC) devices become a key consideration.
SuVolta has invented a device technology that enables dramatic voltage and power scaling while extending the life of planar, bulk CMOS. By reducing the VT variation of the millions of transistors on a chip, the SuVolta Deeply Depleted Channel™ (DDC) technology has a much tighter distribution of threshold voltages and allows for the setting of multiple VTs, which is vital for today’s low-power products.
The benefits of SuVolta’s DDC technology apply across a wide range of IC products, including processors, SOCs and SRAMs.
Details on Fujitsu Semiconductor Limited and SuVolta’s jointly authored IEDM paper demonstrating ultra-low-voltage operation of SRAM down to ~0.4V can be accessed here.
Information on SuVolta’s Deeply Depleted Channel (DDC) technology can be accessed here.
Information on the PowerShrink™ low-power platform can be accessed here.
Get information on the low-power CMOS platform