A developer of CMOS technologies, SuVolta is enabling straightforward power optimization in existing IC's and even greater improvements in new and more aggressive designs. Deeply Depleted Channel™ (DDC) technology is proven and in production as of mid-2013. SuVolta currently has multiple technology development programs with top-tier semiconductor companies, from 65nm to 20nm process nodes. Announced programs are at 28nm and 65nm.
SuVolta has developed a Deeply Depleted Channel (DDC) technology that reduces transistor variability and that is implemented in conventional CMOS. DDC transistor technology enables scaling of two of the most critical transistor parameters – supply voltage, and transistor size to 20nm.
Video: Planar, bulk CMOS advanced
DDC technology enables the reduction of both leakage power and active power consumption, primarily by addressing transistor threshold voltage (VT) variation and carrier mobility issues. Since SuVolta’s technology uses planar, bulk CMOS, it is compatible with existing manufacturing infrastructure, can be integrated into existing processes and is compatible with existing IP and design tools.
Redesign for Low-Voltage, Low-Power Design
The DDC PowerShrink low-power platform provides the ultimate power benefit in polysilicon or High-K Metal Gate (HKMG) process technologies. With PowerShrink, all transistors utilize the DDC technology.
Benefits of the PowerShrink platform include:
- Lower VDD
- 30 - 50% lower active power
- 50 - 60% lower leakage power
14 January 2014
3 September 2013
25 July 2013
23 July 2013
“In a world where mobile applications increasingly dominate, power and cost are the primarily limiters of scaling semiconductor process technologies. SuVolta has developed an innovative way to significantly reduce CMOS transistor active and leakage power. By tightening threshold voltage variability while maintaining performance at lower supply voltage, SuVolta’s platform extends the useful life of bulk planar CMOS processes and the products they enable and negates the need for costly, complex technologies like EUV lithography, FD-SOI or FinFETs. Furthermore, the technology enables companies to preserve and extend the legacy IP blocks they have spent years developing.”
T.J. Rodgers, Founder, President and Chief Executive Officer and Director, Cypress Semiconductor