Read about SuVolta’s thoughts on industry and technology challenges. Below you’ll find links to contributed articles, conference papers and more.
Honey, SuVolta Deeply Depleted My Cortex-M0 Power!
ARM Blog Post
23 July 2013
ARM and SuVolta are collaborating to tackle the low power requirements of emerging and demanding IoT applications and demonstrated quantum leap improvements at the 65nm process node. Read more.
Reducing Transistor Variability For Higher-Performance, Lower-Power Chips
Peer-reviewed Contributed Article
IEEE Micro Magazine
CMOS integrated-circuit, supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance. Read more.
A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits
Fujitsu Semiconductor Ltd. and SuVolta, Inc. paper
2012 International Electron Devices Meeting (IEDM), December 11, 2012
To read the IEDM paper, click here.
System-on-chip technology comes of age
5 October, 2012
SoC technology has been used by fabless vendors and foundries for well over a decade. But it is the rapid proliferation of mobile post-PC products that is proving to be the catalyst for this technology to finally realize its full disruptive potential. Within the last five years, SoC technology has moved from being at the heart of smartphones to enabling tablets and full feature mobile computers like ultrabooks. This article describes the emerging importance of the SoC, its likely technological evolution and its potential impact on the semiconductor industry in a mobility driven age. Read more.
The semiconductor industry needs an economically sensible roadmap that addresses the excessive cost of 20nm and smaller process technologies. This article argues that the semiconductor process technology roadmap should now be split in two: a roadmap with the classical “Moore’s Law” benefit of greater density from shrinking, and a “More-than-Moore” roadmap that enhances the capability of a given process technology by reducing power consumption. Read more.
Reducing Transistor Variability for High Performance Low Power Chips
Hot Chips 24
29 August, 2012
In this presentation Dr. Robert Rogenmoser provides a brief overview of SuVolta’s Deeply Depleted Channel™ (DDC) technology, and focuses on how the technology can be leveraged using circuit design techniques to significantly lower IC power consumption. View video.
Future of CMOS hinges on mobile apps
29 June 2012
In this article, Dr. Scott Thompson has captured his top 10 “points of insight” from the 2012 Symposium on VLSI Technology.
Leading-edge process technology is not economically feasible for a majority of semiconductors, but 'Everything Mobile' has put pressure on every technologist to advance their designs into lower power regimes. In a world where battery life is everything, reducing power consumption is a top priority for every chip company. In this video, we discuss how this can be done with some fairly simple process modifications. View video.
Rethinking the pursuit of Moore's Law
20 June 2012
There is much excitement about the semiconductor industry moving to 28nm and 20nm process technology. For a majority of products, however, it will be several years before these leading-edge process technologies make economic sense. These products will remain on mature process technologies, getting none of the benefits that Moore’s Law brings. What if there was another way? What if you could extend the capabilities of mature technologies without having to overcome the cost wall of a shrink to the leading edge?
This article argues that the benefits of Moore’s Law can now be split in two: the classical benefits of greater density and lower cost-per-transistor from shrinking, and the benefit of extending the capability of mature process technology generations by reducing power consumption. Read more.
How Will the Chip Wars be Won? - Part 1
7 February 2012
How Will the Chip Wars be Won? - Part 2
16 February 2012
As silicon CMOS enters its fifth decade, the industry once again finds itself at a crossroads. At this juncture, the future of CMOS scaling will be defined not only by fundamental device architecture and materials innovations but also the evolving chip landscape. New alliances, players and market segments with radically different cost structures will play a role in determining the future course of the semiconductor industry and the evolution of the semiconductor fabrication process.
Part 1 of this article highlights the emerging importance of the mobile SoC and its impact on the industry landscape and the continued evolution of Moore’s Law.
Part 2 discusses why the new landscape favors an open foundry and design ecosystem and identifies trends that are likely to define the semiconductor industry over the next decade.
Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications
Fujitsu Semiconductor Ltd. and SuVolta, Inc. paper
2011 International Electron Devices Meeting (IEDM), December 7, 2011
Advanced Transistor Technology
ARM TechCon Virtual Event
Archive accessible from 17 November 2011 - 17 May 2012
This session compares FinFET, SOI, and planar bulk technologies at the 22nm node and below. In this talk, Dr. Scott Thompson provides an overview of the technologies, evaluates the advantages and limitations of each, and looks at each technology’s applicability for SoC implementation.
Low Transistor Variability - The Key to Energy Efficient ICs
2nd Berkeley Symposium of Energy Efficient Electronic Systems
3 November 2011
Leakage – It's Worse Than you Think
2 May 2011
As the world uses more and more mobile electronic products, controlling power consumption is the primary limiter of scaling semiconductor process technologies and adding features to integrated circuits.