PST
Technology Overview
Controlling power consumption is a key enabler for adding product features and scaling semiconductor process technologies as the world uses more and more mobile electronics products.
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| Video: Planar, bulk CMOS advanced device technology |
SuVolta's PowerShrink™ low-power CMOS platform significantly lowers power consumption without sacrificing performance across a wide range of integrated circuit (IC) products, including the processors, SRAMs, and SOCs that are critical to today's mobile systems.
SuVolta’s technology lowers both active power and leakage power consumption by decreasing threshold voltage (VT) variation by 50%. This reduced VT variation enables up to 30% scaling of power supply voltage (VDD) while maintaining performance, and eliminates the worst-case tail of the transistor VT distribution that causes the majority of IC product leakage power consumption.
By enabling continued voltage scaling as well as leakage reduction, the SuVolta technology can cut in half the active power consumption of 65nm process technologies as well as reduce leakage power consumption by 5x or more.
EASILY ADOPTABLE
The SuVolta PowerShrink low-power platform is compatible with current manufacturing and design infrastructure.
SuVolta’s Deeply Depleted Channel™ (DDC) transistor leverages existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials. SuVolta’s PowerShrink platform also uses conventional design tools and design flows.
TECHNOLOGY DESCRIPTION
SuVolta’s PowerShrink low-power platform encompasses SuVolta’s Deeply Depleted Channel CMOS transistor, as well as SuVolta’s DDC-optimized circuits and design techniques to take full advantage of the DDC transistor.
SuVolta’s DDC transistor uses a unique channel structure with significant benefits for low power operation compared to conventional transistor technology:
- The DDC transistor enables 30% scaling of supply voltage (VDD) while maintaining performance, and eliminates the worst-case tail of the transistor VT distribution that causes the majority of IC product leakage, by decreasing threshold voltage (VT) variation by 50%
- Click here for more information on VT variation, VDD scaling, and leakage power reduction
- The DDC transistor increases drive current (IEFF) by 10% or more by increasing channel mobility by 30% or more
- IEFF and mobility increases relative to conventional technology at equivalent voltage are even greater when VDD is scaled more than 30%
- The DDC transistor enables better threshold voltage (VT) control through body biasing by increasing body effect by 100% or more
- Click here for more information on body effect and body biasing
SuVolta’s circuits and design techniques take advantage of the unique properties of the DDC transistor to create better circuits than possible with a conventional transistor:
- Smaller, faster IP building blocks that take advantage of the lower variation of the DDC transistor
- Adaptive body biasing to correct systematic manufacturing variations, thus further decreasing VT variation and improving sort yield
- Dynamic body biasing to correct temperature and aging effects
- Dynamic body biasing combined with power modes to enable very low power operation
- Click here for more information on body biasing techniques
RESOURCE LIBRARY
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