DDC PowerShrink™ Platform

The Deeply Depleted Channel™ (DDC) transistor enables lower power operation by reducing power supply voltage and “tightening” the manufacturing corners. The DDC PowerShrink™ platform combines the DDC transistor with SuVolta’s circuit and design techniques, all targeted to match the performance of a conventional process at the same process node, while lowering active and leakage power. Depending on the technology node, circuits using PowerShrink will match the performance of a standard process while demonstrating:

  • 15 - 30% Lower VDD;
  • 30 - 50% lower active power; and
  • 30- 60% lower leakage power.

The DDC PowerShrink platform provides designers the flexibility to either significantly reduce the power consumption of their IC while maintaining performance, or increase operation speed without increasing power consumption.

DDC PowerShrink platform benefits apply across a wide range of IC products, including processors, SoCs and memories.

DDC Technology-Based ARM® Cortex-M0 Processor Test Chip

In an implementation at 65nm, SuVolta’s PowerShrink platform uses the DDC transistor’s improved short-channel effects, lower VT variation, and higher body effect to achieve a 50% reduction in active power and leakage power without compromising performance.

DDC_Power_Performance_ARM_Cortex-M0_chart.jpg

In the implementation, an ARM Cortex-M series processor test chip was manufactured with SuVolta’s DDC PowerShrink platform on a 65nm bulk planar CMOS DDC process.

When compared to an identical ARM Cortex-M0 processor manufactured in the conventional 65nm process, with a 1.2V supply voltage, the DDC transistor-based ARM implementation operating at 0.9V demonstrates the following benefits:

  • 50% lower total power consumption at matched 350MHz operating speed
  • 35% increased operating speed (performance) at matched power
  • 55% increased operating speed when operated at matched supply voltage

Additional benefits include:

  • 40% to 60% less VT variation compared to the baseline transistors in 65nm technology
  • Reduced VT variation leading directly to 200mV lower SRAM VDD-min by improving the VT matching of the transistor pairs in the SRAM cell
  • Twice the transistor body coefficient, by the larger change in VT caused by a given change in body bias voltage (VBB)

DDC PowerShrink Methodology

(as demonstrated in the ARM Cortex-M0 Processor test chip)

Using the PowerShrink methodology involves a re-optimization of threshold voltages and supply voltages to find the optimal speed-power trade-off point. While different implementations may pursue different optimization paths, the following describes the process used for the Cortex-M0 core described above.

Step one: Comparison with baseline

Comparison of the DDC transistor and the baseline (conventional) transistor at the same voltage, with matched threshold voltage.

The DDC transistor has superior performance given its higher effective drive current (IEFF). The DDC universal curve is to the left of the baseline transistor curve, indicating lower delay at matched leakage power (matched VT;sat).

Step_1_-_Comparison_with_the_baseline.jpg

Step two: Voltage is lowered to save active power

At matched threshold voltage, gate overdrive is significantly reduced when supply voltage is lowered. As a result the DDC transistor’s delay is increased.

Step_2_-_Step_two_Voltage_is_lowered_to_save_active_power.jpg

Step three: VT is lowered to match performance

To match performance of the baseline, the DDC device’s VT is lowered. The result is an exponential increase in leakage and matched delay at the slow corner.

Step_3_-_VT_is_lowered_to_match_performance_.jpg

Step four: Body bias is used to save leakage power

In the example implementation at 65nm, body bias is applied to reduce the device’s leakage. Body bias pulls-in the leaky corners to meet the speed spec in order to save leakage power. This achieves a reduction of both active and leakage power while matching the performance of the baseline device.

Step_4_-_Body_bias_is_used_to_save_leakage_power.jpg

Volume Production

The DDC PowerShrink platform is proven and in production as of mid-2013. In addition, SuVolta currently has technology development programs with top-tier semiconductor companies, from 65nm to 20nm process nodes.

Learn More:

mpg4-icon.gif Video: Planar bulk CMOS advanced device technology from SuVolta. View video.

document-icon.gif White paper: entitled "SuVolta's DDC Technology: A Complementary Technology to ARM Embedded Processors for Power Optimized Application". Read white paper.

graphic-icon.gifPress release: First DDC Transistor-Based Chip Enters Volume Production. Read press release.

graphic-icon.gif ARM's blog: "Honey, SuVolta Deeply Depleted my Cortex-M0 Power!", authored by CPU Product Manager, Thomas Ensergieux. Read blog post.

document-icon.gif Technology Brief: VT variation, VDD scaling, and leakage power reduction. Read technology brief.