Deeply Depleted Channel™ (DDC) Low-Power CMOS Technology


	Video: Planar, bulk CMOS advanced device technology

Power consumption is the primary limiter of adding features and functionality on semiconductor chip products ranging from mobile electronics to tethered servers and networking equipment. SuVolta’s Deeply Depleted Channel (DDC) technology enables the reduction of both leakage power and active power consumption, primarily by addressing transistor threshold voltage (V_T) variation and carrier mobility issues. The benefits of SuVolta’s DDC technology apply across a wide range of IC products, including processors, SOCs and SRAMs.

SuVolta’s DDC transistor reduces threshold voltage (V_T) variability and enables continued CMOS scaling. The structure works by forming a deeply depleted channel when a voltage is applied to the gate. In a typical implementation the DDC channel has several regions – an undoped or very lightly doped region, a V_T setting offset region and a screening region. Each implementation of SuVolta’s DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.

The undoped or very lightly doped region removes dopants from the channel which allows for a deeply depleted channel. This reduces random dopant fluctuation (RDF) thereby enabling V_DD scaling and improved mobility for increased effective current.
The V_T setting offset region sets the transistor threshold voltage levels, without degrading channel mobility. This region also improves sigma V_T over conventional transistors.
The screening region screens the charge and sets the depletion layer depth. It also serves as a body for dynamic V_T adjustment through biasing, if desired.

DDC Technology Benefits

The DDC transistor enables lower power operation by enabling reduced power supply voltage. By controlling V_T variation, chips designed using SuVolta DDC technology can achieve a number of benefits including:

30% lower operating voltage with no performance impact
Much lower leakage
Less design “guard banding”
Improved yields

In addition, DDC transistor allows for the setting of multiple V_Ts, which is vital for today’s low-power products.

Besides the benefit of significant V_T variation reduction, DDC transistors have additional benefits which lead to further reductions in power with higher speed. These include:

Increased channel mobility for increased drive current
Reduced drain induced barrier lowering (DIBL)
Increased body coefficient for better V_T control

Power savings is particularly important in embedded SRAM memory blocks. For most chips, lowering supply voltage is limited by the SRAM. By taking advantage of the reduced variability of the DDC transistor, conventional 6T SRAMs have been demonstrated operating below 500mV – amongst the lowest voltage ever reported in a standard embedded SRAM.

SuVolta’s PowerShrink™ low-power platform encompasses SuVolta’s DDC CMOS transistor, as well as SuVolta’s DDC-optimized circuits and design techniques to take full advantage of the DDC transistor.

Learn More

Details on Fujitsu Semiconductor Limited and SuVolta’s jointly authored IEDM paper demonstrating ultra-low-voltage operation of SRAM down to ~0.4V can be accessed here.