Deeply Depleted Channel™ (DDC) Low-Power CMOS Technology
|Video: Planar, bulk CMOS advanced device technology|
Power consumption is the primary limiter of adding features and functionality on semiconductor chip products ranging from mobile electronics to tethered servers and networking equipment. SuVolta’s Deeply Depleted Channel™ (DDC) technology enables the reduction of both leakage power and active power consumption, primarily by addressing transistor threshold voltage (VT) variation and carrier mobility issues. The benefits of SuVolta’s DDC technology apply across a wide range of IC products, including processors, SOCs and memories.
SuVolta’s DDC transistor reduces threshold voltage (VT) variability and enables continued CMOS scaling. The structure works by forming a deeply depleted channel when a voltage is applied to the gate. In a typical implementation the DDC channel has several regions – an undoped or very lightly doped region, a VT setting offset region and a screening region. Each implementation of SuVolta’s DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.
- The undoped or very lightly doped region removes dopants from the channel which allows for a deeply depleted channel. This reduces random dopant fluctuation (RDF) thereby enabling VDD scaling and improved mobility for increased effective current.
- The VT setting offset region sets the transistor threshold voltage levels, without degrading channel mobility. This region also improves sigma VT over conventional transistors.
- The screening region screens the charge and sets the depletion layer depth. It also serves as a body for dynamic VT adjustment through biasing, if desired.
DDC Technology Benefits
The DDC transistor enables lower power operation by reducing power supply voltage. DDC technology provides designers the flexibility to either significantly reduce the power consumption of their IC while maintaining performance, or dramatically increase operation speed without increasing power consumption.
Chips designed using SuVolta's DDC technology can achieve a number of benefits including:
- As much as 50% total power reduction while matching the operating speed of the same circuit implemented in conventional transistors
- As much as 35% operating speed improvement while matching the power consumption of the conventional design
- Transistor variability cut by as much as 40% and more, improving memory performance and manufacturability
- Superior analog circuit performance
Use of DDC transistors allows for the setting of multiple VTs, which is vital for today’s low-power products and complex chip devices.
Besides the benefit of significant VT variation reduction, DDC transistors have additional benefits which lead to further reductions in power with higher speed. These include:
- Increased channel mobility for increased drive current
- Reduced drain induced barrier lowering (DIBL)
- Increased body coefficient for better VT control
Power savings is particularly important in embedded SRAM memory blocks. For most chips, lowering supply voltage is limited by the SRAM. By taking advantage of the reduced variability of the DDC transistor, conventional 6T SRAMs have been demonstrated operating below 500mV – amongst the lowest voltage ever reported in a standard embedded SRAM.
DDC Technology Options
The DDC PowerShrink low-power platform encompasses SuVolta's DDC CMOS transistor, as well as SuVolta's circuits and design techniques that take full advantage of the DDC transistor. The PowerShrink platform provides the ultimate power and performance benefit. With PowerShrink, all transistors utilize the DDC technology. The PowerShrink platform can be integrated with both polysilicon and High-K Metal-Gate (HKMG) process technologies. Benefits include:
- Lower VDD
- 30 - 50% lower active power
- 50 - 60% lower leakage power
The DDC DesignBoost transistor swap implementation approach works with existing design databases where subsets of the transistors are replaced with DDC transistors. Benefits of this approach include:
- Lower leakage power up to 50%
- Reduced SRAM VDD-MIN
Typical applications of the DesignBoost option include:
- Replacing the leakier transistors with DDC transistors, or
- Replacing SRAM bitcell transistors with DDC transistors to improve performance and lower minimum operating voltage (VDD-MIN)
White paper entitled "SuVolta's DDC Technology: A Complementary Technology to ARM Embedded Processors for Power Optimized Application" can be accessed here.
First DDC Transistor-Based Chip Enters Volume Production. Read more.
ARM's blog "Honey, SuVolta Deeply Depleted my Cortex-M0 Power!", authored by CPU Product Manager, Thomas Ensergieux. Read post.
UMC and SuVolta Announce Joint Development of 28nm Low-Power Process Technology. Read more.
SuVolta Announces Speed-Power Benefits of Transistor Technology Validated in ARM Processor. Read more.
Details on Fujitsu Semiconductor Limited and SuVolta’s jointly authored 2012 IEDM paper demonstrating a highly integrated 65-nm SoC process with enhanced power/performance of Digital and Analog circuits can be accessed here.
Details on Fujitsu Semiconductor Limited and SuVolta’s jointly authored IEDM paper demonstrating ultra-low-voltage operation of SRAM down to ~0.4V can be accessed here.
A graphic of an example implementation of SuVolta's Deeply Depleted Channel (DDC) transistor can be viewed here.
Links to technology briefs, white papers and more.
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