Resource Library

Get information on SuVolta and Deeply Depleted Channel™ (DDC) bulk, planar CMOS technology. Below you’ll find links to technology briefs, conference papers, videos and more.

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Videos

Get information about SuVolta's technology and how it solves the industry's greatest challenge - power.


mpg4-icon.gifView Video Describing SuVolta's Low-Power CMOS-based Technology

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Blog Posts

Read what others are saying about SuVolta's technology, circuits and design techniques.

document-icon.gifARM: "Honey, SuVolta Deeply Depleted My ARM Cortex-M0 Power!", authored by CPU Product Manager, Thomas Ensergueix.

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White Papers

Get information about SuVolta’s technology, circuits and design techniques.

document-icon.gifSuVolta's DDC Technology: A Complementary Technology to ARM Embedded Processors for Power Optimized Application

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Technology Briefs

Get information about SuVolta’s technology, circuits and design techniques.

document-icon.gifTransistor VT Variation, VDD Scaling, and Leakage Technology Brief

document-icon.gifBody Effect and Body Biasing Technology Brief

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Conference Papers and Presentations

View conference papers and presentations that SuVolta has authored or co-authored.

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2013 IEEE Custom Integrated Circuits Conference (CICC) 

document-icon.gif     Paper: Low Power ARM® Cortex™-M0 CPU and SRAM Using Deeply Depleted Channel (DDC) Transistors with VDD Scaling and Body Bias

document-icon.gif     Paper: A Slew-Rate Based Process Monitor and Bi-directional Body Bias Circuit for Adaptive Body Biasing in SoC Applications

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2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)

document-icon.gif     Paper: SRAM Cell Optimization for Low AVT Transistors (Best-paper winner)

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2013 HotChips25: A Symposium on High Performance Chips

SOC Session 

powerpoint-icon.gifPresentation: 50% Lower Power ARM Cortex CPU using DDC Transistors with Body Bias

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2013 Semicon Korea

document-icon.gif     Paper: CMOS Scaling from 28nm to 10nm Through High Mobility Channel Engineering: Challenges & Solutions

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2012 IEEE International Electron Devices Meeting (IEDM) 
Fujitsu Semiconductor Ltd. and SuVolta, Inc. jointly-authored paper

document-icon.gif     Paper: A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits

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2011 International Electron Devices Meeting (IEDM)
Fujitsu Semiconductor Ltd. and SuVolta, Inc. jointly-authored paper

document-icon.gifPaper: Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications


powerpoint-icon.gifPresentation: Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications

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2nd Berkeley Symposium of Energy Efficient Electronic Systems

document-icon.gifLow Transistor Variability - The Key to Energy Efficient ICs

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Miscellaneous

graphic-icon.gifInfographic incorporating PricewaterhouseCoopers MoneyTree™ Report on venture capital funding for the semiconductor industry.