As the world uses more and more mobile electronics products, controlling power consumption while managing performance and cost is key for adding features and scaling process technologies. SuVolta has defined a flexible and cost-effective device technology option, extending the benefits of CMOS technology.
|Video: Planar, bulk CMOS advanced device technology|
Deeply Depleted Channel™ (DDC) technology provides designers flexibility, across a wide range of integrated circuit (IC) products, including processors, memories, and SOCs that are critical to today's mobile systems.
SuVolta’ technology has been demonstrated to:
- Reduce total power consumption by as much as 50% while matching the operating speed of the same circuit implemented in conventional transistors
- Increased operating speed (performance) by as much as 35% while matching the power consumption of the conventional design
- Cut transistor variability by as much as 40% and more, improving memory performance and manufacturability
- Enable superior analog circuit performance
SuVolta is working with multiple top-tier semiconductor companies at 20nm and 28nm and has announced silicon results of its technology at 65nm/55nm nodes.
At 65nm, SuVolta’s technology has been demonstrated to lower both active power and leakage power consumption by decreasing threshold voltage (VT) variation by as much as 50%. This reduced VT variation enables up to 30% scaling of power supply voltage (VDD) while maintaining performance, and eliminates the worst-case tail of the transistor VT distribution that causes the majority of IC product leakage power consumption.
By enabling continued voltage scaling as well as leakage reduction, the SuVolta technology can cut in half the power consumption of 65nm process technologies.
Deeply Depleted Channel (DDC) technology is compatible with current manufacturing and design infrastructure.
The DDC technology leverages existing CMOS design rules and process techniques, and can be manufactured in existing fabs because it does not require new equipment or new materials. In addition, the technology can use conventional design tools and design flows.
DDC Technology Options
The DDC PowerShrink™ low-power platform encompasses SuVolta’s DDC CMOS transistor, as well as SuVolta’s circuits and design techniques that take full advantage of the DDC transistor. The PowerShrink platform provides the ultimate power and performance benefit. With PowerShrink, all transistors utilize the DDC technology. The PowerShrink platform can be integrated with both polysilicon or High-K Metal-Gate (HKMG) process technologies. Benefits include:
- Lower VDD
- 30 - 50% lower active power
- 50 - 60% lower leakage power
The DDC DesignBoost transistor swap implementation approach works with existing design databases where a subset of the transistors are replaced with DDC transistors. Benefits of this approach include:
- Lower leakage power up to 50%
- Reduced SRAM VDD-MIN
Typical applications of the DesignBoost option include:
- Replacing the leakier transistors with DDC transistors, or
- Replacing SRAM bitcell transistors with DDC transistors to improve performance and lower minimum operating voltage (VDD-MIN)
SuVolta’s DDC transistor uses a unique channel structure to achieve significant benefits for low power operation compared to conventional transistor technology:
- Enables 30% scaling down of supply voltage (VDD) while maintaining performance, and eliminates the worst-case tail of the transistor VT distribution that causes the majority of IC product leakage, by decreasing threshold voltage (VT) variation by as much as 50%
- Click here for more information on VT variation, VDD scaling, and leakage power reduction
- Increases drive current (IEFF) by 10% or more by increasing channel mobility by 30% or more
- Even greater IEFF and mobility increases realized when VDD is scaled more than 30%
- Achieves better threshold voltage (VT) control through body biasing enabled by significantly increased body effect
- Click here for more information on body effect and body biasing
SuVolta’s circuits and design techniques take advantage of the unique properties of the DDC transistor to create better circuits than possible with a conventional transistor:
- Smaller, faster IP building blocks that take advantage of the lower variation of the DDC transistor
- Adaptive body biasing to correct systematic manufacturing variations, thus further decreasing VT variation and improving sort yield
- Dynamic body biasing to correct temperature and aging effects
- Dynamic body biasing combined with power modes to enable very low power operation
- Click here for more information on body biasing techniques