DDC Technology Overview

Power dissipation has become possibly the foremost architectural limiter for mobile SoCs (system on chips) constraining both thermal envelope and battery life. Supply voltage (VDD) scaling used to be the most effective design lever to reduce power. In recent deep submicron nodes, however, increasing systematic and random transistor variations (e.g., random dopant fluctuation) limit the ability to scale threshold voltage (VT), in turn limiting VDD reduction. In particular, VDD scaling has been limited by SRAM VDDmin yield.

SuVolta’s Deeply Depleted Channel™ (DDC) technology was invented to create a low-variability, low-power optimized transistor in bulk, planar CMOS.


Video: Planar, bulk CMOS advanced device technology

By controlling VT variation, chips designed using DDC technology can achieve a number of benefits including:

  • up to 30 percent lower operating voltage with no performance impact;
  • lower leakage;
  • less design “guard banding”; and
  • improved yields.

Besides the benefit of significant VT variation reduction, DDC transistors have additional benefits which lead to further reductions in power while maintaining circuit speed. These include:

  • increased channel mobility for increased drive current;
  • reduced drain induced barrier lowering (DIBL); and
  • increased body coefficient for finer VT control.

DDC technology allows for the setting of multiple VTs, which is vital for today’s low-power products. The benefits of the DDC technology apply across a wide range of IC products, including processors, SoCs and memories.

DDC Technology Structure

The structure works by forming a deeply depleted channel when a voltage is applied to the gate. Each implementation of the DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.


Total SRAM VT variation is 40-60% lower on 65nm DDC technology than 65nm baseline technology.

In a typical implementation the DDC channel has several regions in the silicon substrate under the transistor gate oxide – an undoped or very lightly doped region, a VT setting offset region and a screening region.

  • The top layer is a low-doped channel layer usually made by silicon epitaxial deposition. This layer dramatically reduces VT variation (VT) by reducing random dopant fluctuation (RDF).
  • The VT setting layer enables multiple threshold voltages without adding dopants to the channel region.
  • The screening layer terminates the depletion layer in the channel to provide a uniform depletion layer and excellent short-channel effects. The deep layers combine to produce a strong transistor body coefficient that enables many circuit-level power reduction techniques.

DDC Technology Benefits in SRAMs

Power savings is particularly important in embedded SRAM memory blocks. For most chips, lowering supply voltage is limited by the SRAM’s minimum operating voltage (Vmin). By taking advantage of the reduced variability of the DDC transistor, 6T SRAMs using DDC technology have been demonstrated operating at 150mV to 250mV below identical SRAMs implemented in conventional CMOS technology.


DDC technology lowers VDD-min of 8Mb SRAM by 150mV at 125°C -- Lower SRAM VDD-min Enables Low-Voltage Operation

Demonstration Example

DDC transistors implemented in 65nm process technology demonstrate 40% to 60% less VT variation compared to the baseline transistors in 65nm technology. The reduced VT variation leads directly to lower SRAM VDD-min by improving the VT matching of the transistor pairs in the SRAM cell.


DDC technology lowers VDD-min of 8Mb SRAM by 150mV at 125°C -- Lower SRAM VDD-min Enables Low-Voltage Operation

Integrates with Existing Fabs and Design Flows

DDC technology is compatible with current manufacturing and design infrastructure. The most integrate-able of all emerging transistor types, DDC technology leverages existing CMOS design rules and process techniques, can be manufactured in existing fabs, uses conventional design tools and flows, and does not require new equipment or new materials.

Volume Production

DDC technology is proven and in production as of mid-2013. In addition, SuVolta currently has technology development programs with top-tier semiconductor companies, from 65nm to 20nm process nodes.

Learn More:

graphic-icon.gifPress Release: First DDC Transistor-Based Chip Enters Volume Production. Read press release.

graphic-icon.gifARM blog post: "Honey, SuVolta Deeply Depleted my Cortex-M0 Power!", authored by CPU Product Manager, Thomas Ensergieux. Read blog post.

document-icon.gif White paper: "SuVolta's DDC Technology: A Complementary Technology to ARM Embedded Processors for Power Optimized Application". Read white paper.