A developer of CMOS technologies, SuVolta is enabling straightforward power optimization in existing IC's and even greater improvements in new and more aggressive designs. Deeply Depleted Channel™ (DDC) technology is proven and in production as of mid-2013. SuVolta currently has multiple technology development programs with top-tier semiconductor companies, from 65nm to 20nm process nodes. Announced programs are at 28nm and 65nm.
SuVolta has developed a Deeply Depleted Channel (DDC) technology that reduces transistor variability and that is implemented in conventional CMOS. DDC transistor technology enables scaling of two of the most critical transistor parameters – supply voltage, and transistor size to 20nm.
Video: Planar, bulk CMOS advanced
DDC technology enables the reduction of both leakage power and active power consumption, primarily by addressing transistor threshold voltage (VT) variation and carrier mobility issues. Since SuVolta’s technology uses planar, bulk CMOS, it is compatible with existing manufacturing infrastructure, can be integrated into existing processes and is compatible with existing IP and design tools.
Redesign for Low-Voltage, Low-Power Design
The DDC PowerShrink low-power platform provides the ultimate power benefit in polysilicon or High-K Metal Gate (HKMG) process technologies. With PowerShrink, all transistors utilize the DDC technology.
Benefits of the PowerShrink platform include:
- Lower VDD
- 30 - 50% lower active power
- 50 - 60% lower leakage power
14 January 2014
3 September 2013
25 July 2013
23 July 2013
“Designers traditionally reduce the power their chips consume by shrinking the dimensions of transistors in their chips, but the expense incurred in moving to smaller geometries escalates with each technology node. SuVolta’s novel transistor design reduces power by a factor of two without shrinking the size of the transistor. This enables a mature 65nm process to deliver performance per watt characteristics comparable to advanced 32nm processes. SuVolta’s innovation should appeal especially to semiconductor suppliers who want to reduce the power their chips consume, or to increase performance within a fixed power budget, but don’t need the higher transistor density a smaller process geometry enables. While some argue that the industry must move to 3-D transistor structures now, SuVolta shows that rumors of the death of the planar transistor have been greatly exaggerated.”
Nathan Brookwood, Research Fellow, Insight64