A developer of CMOS technologies, SuVolta is enabling straightforward performance- power optimization in existing IC's and even greater improvements in new and more aggressive designs. The Deeply Depleted Channel™ (DDC) technology is proven and in production as of mid-2013. SuVolta currently has six technology development programs with top-tier semiconductor companies, from 65nm to 20nm process nodes. Announced programs are at 28nm and 65nm. Learn more.
SuVolta has developed a Deeply Depleted Channel (DDC) technology that reduces transistor variability and that is implemented in conventional CMOS. DDC transistor technology enables scaling of two of the most critical transistor parameters – supply voltage, and transistor size to 20nm and below.
Video: Planar, bulk CMOS advanced
DDC technology enables the reduction of both leakage power and active power consumption, primarily by addressing transistor threshold voltage (VT) variation and carrier mobility issues. Since SuVolta’s technology uses planar, bulk CMOS, it is compatible with existing manufacturing infrastructure, can be easily integrated into existing processes and is compatible with existing IP and design tools.
For the ultimate power-performance benefit, DDC™ technology can be adopted in all transistors in a design. Or, DDC technology can be adopted across a subset of transistors to reduce leakage power and SRAM minimum operating voltage.
Redesign for Low-Voltage, Low-Power Design
The DDC PowerShrink low-power platform provides the ultimate power and performance benefit in polysilicon or High-K Metal Gate (HKMG) process technologies. With PowerShrink, all transistors utilize the DDC technology.
Benefits of the PowerShrink platform include:
- Lower VDD
- 30 - 50% lower active power
- 50 - 60% lower leakage power
Same Design – Replace leaky transistors + SRAM bitcell
The DDC DesignBoost transistor swap works with existing design databases where a subset of the transistors are replaced with DDC transistors.
Benefits of this approach include:
- Lower leakage power up to 50%
- Reduced SRAM VDD-MIN
Typical applications of the DesignBoost option include:
- Replacing the leakier transistors with DDC transistors that could cut leakage, or
- Replacing SRAM bitcell transistors with DDC transistors to improve performance and lower minimum operating voltage, VDD-MIN
10 September 2013
3 September 2013
25 July 2013
23 July 2013
“SuVolta’s low-power platform could have a dramatic impact on the industry. The substantial device matching improvement of core and IO devices, enhanced body effect and perceived ‘simple’ integration with a digital CMOS manufacturing flow are momentous and could have a dramatic impact on reducing power and cost of highly-integrated SoCs.”
Pieter Vorenkamp, Senior Vice President, Operations Engineering, Operations and Central Engineering, Broadcom Corporation